VSyn - Generation of SA/VHDL/RTL to VHDL for
synthesis
VSyn is Windows program originally specified and funded by Nokia Cellular System (NCS) and VTT Electronics at a sub project of ESV Programme. The tool is entirely implemented, produced and further developed by Dactronics Oy.
SA/VHDL/RTL is a method developed by NCS and VTT to manage and
generate VHDL models for synthesis with a CASE tool.
VSyn generates from the graphical SA/VHDL/RTL a full hierarchical VHDL
model for synthesis.
SA bubbles represent VHDL components: entity name=file name
Only the hierarchy of the VHDL model is needed to draw with SA. Signal definitions are picked by VSyn from included or hand written VHDL models
