BSDL
-- =========================================================
-- IRC definitions. Results go to file IRC.OUT
-- =========================================================
7 EXTEST -- this leads to WARNING, but EXTEST for 0 will be defined also
2 SAMPLE
1 IDCODE F FFFF 7FA 1 -- HEX values for version, part nr & vendor + 1
--3 MYFLA1 DR -- signal MYFLA1 available to CORE (not to PADS)
--4 MYCKDR CKDR -- CLockMYCKDR, ShiftMYCKDR etc. generated
--5 MYFLA2 DR
14 BYPASS -- sorry this is not the last one
-- =========================================================
-- Start of PAD CONNECTION LIST (BS CELLS from TAP to TAP)
-- =========================================================
XX(8:1) OUT (47,46,45,44,43,42,41,40) ENXX /PADXX-- this is the bus syntax for BSDL output
XXI(8:1) IN PADXX
YY(1:3) OUT (39,38,37) ENYY -- this may work, but please use downto !
ENXX OUT control_safe0 -- this is a control for BX pad with 0 value for Hi-Z to XX
ENYY OUT control_safe1 -- this is a control for BX pad with 1 value for Hi-Z to YY
A00 IN 10 /ASTART
A01 IN 11
A02 IN 12
A03 IN 13
BXOUT OUT 14 ENBX /BX -- this BXOUT output BS cell for BX inout pad with threestate enable ENBX
BXIN IN BX -- this is input BS cell from BX inout pad, physical pin from BX = 14
ENBX OUT control
-- word control, control_safe1 or control_safe0 must be used to make a difference with normal output
ENBXOUT OUT 15
A06 OUT 3
A07 OUT 4
A08 OUT 5
A09 OUT 6
-- ************ BSDL DEFINITIONS **************
-- BSDL definition part must be at the end of this DEF file -
-- after start of first BSDL definition all IRC or BS CELL definitions ignored !
LINKAGE ENTITY -- all the text directly copied to the end of entity
NC :linkage bit_vector(1 to 5);
VDD :linkage bit_vector(1 to 8);
GND :linkage bit_vector(1 to 13) );
END LINKAGE ENTITY -- notice different end at last line: 2 x ')' and ; It is end of port.
-- Use same pin nr twice on bs cell definitions and linkage/tap pin maps to get error
LINKAGE PIN_MAP_STRING -- all the text directly copied to the end of PIN_MAP_STRING
"NC:(20,21,22,23,24)," &
"VDD:(16,17,18,19,25,26,27,28)," &
"GND:(1,2,7,8,9,29,30,31,32,33,34,35,36)";
END LINKAGE PIN_MAP_STRING -- notice different end at last line
TAP PIN_MAP_STRING -- all the text directly copied to the end of PIN_MAP_STRING
"TRST :52," &
"TCK :51," &
"TMS :50," &
"TDI :49," &
"TDO :48," &
END TAP PIN_MAP_STRING -- notice that all the lines end similiarly with ," &
-- ********* END OF BSDL DEFINITIONS **********
OUTPUT: Generated VHDL synthesis model of the Instruction Register and the whole VHDL of the Boundary Scan logic. Also
BSDL model of the ASIC is generated to be utilized with Automatic Test Pattern Generation (ATPG) and Automatic Test Equipment (ATE) tools.
Click here to see BSDL output.
BSGEN has been implemented with an open architecture. BSGEN reads VHDL source for BS cells from selected library directory below install directory. User can define new libraries with different cell styles or clocking. Two libraries are included in the basic release: basic library without INTEST and BIST features and its synchronized version.
Top level part of the compiled VHDL model can be used as a symbol for schematic work when connecting JTAG implementation of the ASIC core to the pads of the ASIC.
BSGEN also allows clocking strategies with boundary scan register. Clock skew for a long register (flip flop for each ASIC I/O pin) can be avoided by allowing BSGEN to split register to smaller parts which are separated with opposite clocked flip flop.
Availabilty: As a PC/DOS program license with or without Windows interface.
GAWK filtersources available for processing input file from any ASCII-listing of pin names. Separate BSGEN compilations with technical consultation also available.
References: succesfully used in the industry (Nokia Cellular Systems in Finland) from the beginning of the year 1993 with Synopsys Design Compiler (reg. TM of Synopsys Inc)
