OUTPUT: Generated VHDL synthesis model of the Instruction Register and the whole VHDL of the Boundary Scan logic. Also
BSDL model of the ASIC is generated to be utilized with Automatic Test Pattern Generation (ATPG) and Automatic Test Equipment (ATE) tools.
Click here to see BSDL output.
--------------------------------------------------------------------
-- -
-- BSGEN v2.07 Boundary Scan VHDL/BSDL Code Generator -
-- (C) 1997 Dactronics Oy, All Rights Reserved. -
-- -
--------------------------------------------------------------------
-- This code has been generated 5.10.1997 21:00:13
-- from file: C:\MSIP\BSGEN\EXAMPLES\SMALL.DEF
--------------------------------------------------------------------
entity SMALL is
generic(PHYSICAL_PIN_MAP : string := "PQFP_PACKAGE");
port(
TRST :in bit ;
TCK :in bit ;
TMS :in bit ;
TDI :in bit ;
TDO :out bit ;
PADXX8 :inout bit ;
PADXX7 :inout bit ;
PADXX6 :inout bit ;
PADXX5 :inout bit ;
PADXX4 :inout bit ;
PADXX3 :inout bit ;
PADXX2 :inout bit ;
PADXX1 :inout bit ;
YY1 :inout bit ;
YY2 :inout bit ;
YY3 :inout bit ;
ASTART :in bit ;
A01 :in bit ;
A02 :in bit ;
A03 :in bit ;
BX :inout bit ;
ENBXOUT :out bit ;
A06 :out bit ;
A07 :out bit ;
A08 :out bit ;
A09 :out bit ;
NC :LINKAGE BIT_VECTOR(1 TO 5);
VDD :LINKAGE BIT_VECTOR(1 TO 8);
GND :LINKAGE BIT_VECTOR(1 TO 13) );
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of SMALL:entity is "STD_1149_1_1993"; -- STD_1149_1_1990 if 1993 rules not oboyed
attribute PIN_MAP of SMALL:entity is PHYSICAL_PIN_MAP;
-- BSGEN 2.0: maximum pin nr defined (package size?) = 52
constant PQFP_PACKAGE:PIN_MAP_STRING:=
"TRST :52," &
"TCK :51," &
"TMS :50," &
"TDI :49," &
"TDO :48," &
-- should we put next TAP attributes to def file ?
attribute TAP_SCAN_IN of TDI: signal is true;
attribute TAP_SCAN_MODE of TMS: signal is true;
attribute TAP_SCAN_OUT of TDO: signal is true;
attribute TAP_SCAN_CLOCK of TCK: signal is (10.0e6,BOTH);
attribute TAP_SCAN_RESET of TRST: signal is true;
attribute INSTRUCTION_LENGTH of SMALL : entity is 4;
attribute INSTRUCTION_OPCODE of SMALL : entity is
"IDCODE (0001)," &
"SAMPLE (0010)," &
"EXTEST (0000, 0111)," &
"BYPASS (0011, 0100, 0101, 0110, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111)";
attribute INSTRUCTION_CAPTURE of SMALL : entity is
"0001";
attribute IDCODE_REGISTER of SMALL : entity is
"1111" & -- Version "1111"
"1111111111111111" & -- Part Number
"11111111010" & -- 11 bit manufacture ID# "11111111010"
"1"; -- mandatory LSB
-- SMALL has no private instructions.
-- no attribute REGISTER_ACCESS needed with BSGEN, if no user defined registers (only private)
-- attribute BOUNDARY_CELLS of SMALL : entity is "BC_1, BC_4";
attribute BOUNDARY_LENGTH of SMALL : entity is 33;
attribute BOUNDARY_REGISTER of SMALL : entity is
-- num cell port function safe [ccell disval rslt]
" 0(BC_1, PADXX8, output3, X,19,0,Z),"& -- cell 19 set to 0 controls this to Hi-Z
" 1(BC_1, PADXX7, output3, X,19,0,Z),"& -- cell 19 set to 0 controls this to Hi-Z
" 2(BC_1, PADXX6, output3, X,19,0,Z),"& -- cell 19 set to 0 controls this to Hi-Z
" 3(BC_1, PADXX5, output3, X,19,0,Z),"& -- cell 19 set to 0 controls this to Hi-Z
" 4(BC_1, PADXX4, output3, X,19,0,Z),"& -- cell 19 set to 0 controls this to Hi-Z
" 5(BC_1, PADXX3, output3, X,19,0,Z),"& -- cell 19 set to 0 controls this to Hi-Z
" 6(BC_1, PADXX2, output3, X,19,0,Z),"& -- cell 19 set to 0 controls this to Hi-Z
" 7(BC_1, PADXX1, output3, X,19,0,Z),"& -- cell 19 set to 0 controls this to Hi-Z
" 8(BC_4, PADXX8, input, X),"&
" 9(BC_4, PADXX7, input, X),"&
" 10(BC_4, PADXX6, input, X),"&
" 11(BC_4, PADXX5, input, X),"&
" 12(BC_4, PADXX4, input, X),"&
" 13(BC_4, PADXX3, input, X),"&
" 14(BC_4, PADXX2, input, X),"&
" 15(BC_4, PADXX1, input, X),"&
" 16(BC_1, YY1, output3, X,20,1,Z),"& -- cell 20 set to 1 controls this to Hi-Z
" 17(BC_1, YY2, output3, X,20,1,Z),"& -- cell 20 set to 1 controls this to Hi-Z
" 18(BC_1, YY3, output3, X,20,1,Z),"& -- cell 20 set to 1 controls this to Hi-Z
" 19(BC_1, *, control, 0),"& -- safe value 0 controls outputs to Hi-Z
" 20(BC_1, *, control, 1),"& -- safe value 1 controls outputs to Hi-Z
" 21(BC_4, ASTART, input, X),"&
" 22(BC_4, A01, input, X),"&
" 23(BC_4, A02, input, X),"&
" 24(BC_4, A03, input, X),"&
" 25(BC_1, BX, output3, X,27,1,Z),"& -- cell 27 set to 1 controls this to Hi-Z
" 26(BC_4, BX, input, X),"&
" 27(BC_1, *, control, 1),"& -- safe value 1 controls outputs to Hi-Z
" 28(BC_1, ENBXOUT, output2, X),"&
" 29(BC_1, A06, output2, X),"&
" 30(BC_1, A07, output2, X),"&
" 31(BC_1, A08, output2, X),"&
" 32(BC_1, A09, output2, X)";
end SMALL;
BSGEN has been implemented with an open architecture. BSGEN reads VHDL source for BS cells from selected library directory below install directory. User can define new libraries with different cell styles or clocking. Two libraries are included in the basic release: basic library without INTEST and BIST features and its synchronized version.
Top level part of the compiled VHDL model can be used as a symbol for schematic work when connecting JTAG implementation of the ASIC core to the pads of the ASIC.
BSGEN also allows clocking strategies with boundary scan register. Clock skew for a long register (flip flop for each ASIC I/O pin) can be avoided by allowing BSGEN to split register to smaller parts which are separated with opposite clocked flip flop.
Availabilty: As a PC/DOS program license with or without Windows interface. GAWK filtersources available for processing input file from any ASCII-listing of pin names. Separate BSGEN compilations with technical consultation also available.
References: succesfully used in the industry (Nokia Cellular Systems in Finland) from the beginning of the year 1993 with Synopsys Design Compiler (reg. TM of Synopsys Inc)
