OUTPUT: Generated VHDL synthesis model of the Instruction Register and the whole VHDL of the Boundary Scan logic. Also
BSDL model of the ASIC is generated to be utilized with Automatic Test Pattern Generation (ATPG) and Automatic Test Equipment (ATE) tools.
Click here to see BSDL output.
--------------------------------------------------------------------
-- -
-- BSGEN v2.06 Boundary Scan VHDL/BSDL Code Generator -
-- (C) 1997 Dactronics Oy, All Rights Reserved. -
-- -
--------------------------------------------------------------------
-- This code has been generated 19.4.1997 9:03:20
-- from file: C:\BSGEN2\EXAMPLES\SMALL.DEF
--------------------------------------------------------------------
--===== BSGEN v2.0: Start of Filtered C:\BSGEN\1\TAP1.VHD
ENTITY TAP1 IS
PORT
(
MYFLA1 : OUT bit;
MYFLA2 : OUT bit;
FromMYCKDR : IN bit;
ClockMYCKDR : OUT bit;
ShiftMYCKDR : OUT bit;
UpdateMYCKDR : OUT bit;
OPadMC : OUT bit;
ShiftBSDR : OUT bit;
ClockBSDR : OUT bit;
UpdateBSDR : OUT bit;
FromDR : IN bit;
TDO : OUT bit;
ENABLE : OUT bit; -- is enable for TDO
TDI : IN bit;
TMS : IN bit;
TCK : IN bit;
TRST : IN bit
);
END TAP1;
ARCHITECTURE Behavior OF TAP1 IS
-- BSGEN v2.0: IRC CONSTANT DEFINITIONS
-- Check from irc.out these and process Handle_IR (also in irc.vhd)
CONSTANT IRC_LEN : natural := 4;
CONSTANT IRC_RESET : bit_vector(IRC_LEN - 1 DOWNTO 0) := "0001";
CONSTANT IDCODE : bit_vector(31 DOWNTO 0) := B"1111_1111111111111111_11111111010_1" ;
-- end of CONSTANTS
BSGEN has been implemented with an open architecture. BSGEN reads VHDL source for BS cells from selected library directory below install directory. User can define new libraries with different cell styles or clocking. Two libraries are included in the basic release: basic library without INTEST and BIST features and its synchronized version.
Top level part of the compiled VHDL model can be used as a symbol for schematic work when connecting JTAG implementation of the ASIC core to the pads of the ASIC.
BSGEN also allows clocking strategies with boundary scan register. Clock skew for a long register (flip flop for each ASIC I/O pin) can be avoided by allowing BSGEN to split register to smaller parts which are separated with opposite clocked flip flop.
Availabilty: As a PC/DOS program license with or without Windows interface. GAWK filtersources available for processing input file from any ASCII-listing of pin names. Separate BSGEN compilations with technical consultation also available.
References: succesfully used in the industry (Nokia Cellular Systems in Finland) from the beginning of the year 1993 with Synopsys Design Compiler (reg. TM of Synopsys Inc)
